This Schottky-clamped circuit is designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize effects of system decoding. When used with high-speed memories, the delay time of this decoder is usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The DM74LS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.This decoder/demultiplexer features fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design.
Features
Designed specifically for high-speed memory decoders and data transmission systems
Incorporates 3 enable inputs to simplify cascading and/or data reception
Schottky clamped for high performance
Typical propagation delay (3 levels of logic): 21ns
