Each of these data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR invert gates. Separate strobe inputs are provided for each of the two four-line sections.
Permits multiplexing from N lines to 1 line
Performs at parallel-to-serial conversion
Strobe (enable) line provided for cascading (N lines to n lines)